Assisted GPS (5 of 7)

Flexible Design. Figure 2 illustrates an alternative organization designed to address these issues. In this case, the signal processing of each bin is much more sophisticated, and hence the entire search engine no longer lends itself to hardware mechanization. Instead, it is best implemented as a set of correlator channels each with multiple fingers. By using multiple channels together, one or more larger search engines can be built up as needed to span the required code-phase search range.

Figure 2: A two-code-phase subATTO search engine. In addition to the operational blocks described in Figure 1, the ACV (autoconvolution) block constitutes a proprietary algorithm utilizing multiple fast Fourier transform (FFT) bins. The FFT/ACV/squarer process provides improved sensitivity for the same overall integration period compared to the technique of Figure 1.

This arrangement draws on the patented subATTO signal processing technology (see side bar), which facilitates coherent integration over much longer intervals than a bit period. It results in shorter integration periods being used to achieve the same sensitivity. Since this more-flexible architecture also allows all of the hardware resources to be effective all of the time during acquisition, it results in far more cost-effective use of hardware to achieve the required sensitivity and acquisition time.

This approach has been employed using two very different hardware architectures. In the uN8130 baseband processor, a modestly dimensioned hardware search engine is used in tandem with 12 correlator channels comprising four fingers each. The correlators are used for both acquisition and tracking while the search engine performs the more difficult task in acquiring the first satellite and some of the subsequent satellites. Whenever the search engine acquires a signal, it passes it to one of the correlators. This solution has been adapted successfully for both CDMA and GSM operation, with performance well in excess of the standards.

In another example, flexible correlator hardware resources have been incorporated into a chip designed to operate with a host processor. subATTO processing takes place on the host. A search strategy was devised that keeps the hardware working close to its maximum potential throughout the acquisition phase. The resulting performance is well in excess of the standards yet again with minimal hardware costs. This approach demands much more general purpose processing capacity but much less dedicated hardware support.

Figure 3: Core signal-processing scheme. The fast Fourier transform (FFT) block is equivalent to the ensemble of local oscillators, second mixers, and first summers of Figure 2, while the windowing and eliminate data blocks correspond to the ACV (autoconvolution) block in Figure 2. Various estimation algorithms are employed depending on the implementation.

Acquisition Strategies.
We have developed a range of strategies to suit GSM and CDMA standards–based assistance schemes and the hardware architectures previously described. These involve the signal processing schemes described above as well as bit-synchronous signal processing schemes (when bit synchronization is feasible) using both correlators and search engines. We are also working with our chipset partners to optimize their hardware architectures to suit advanced acquisition strategies to improve sensitivity and acquisition time. One example is the use of multiple smaller search engines combined with correlators. This is an ideal compromise when general purpose processing capacity is limited.

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